Article ID: 000097864 Content Type: Troubleshooting Last Reviewed: 02/20/2024

Why does the Intel Agilex® 7 F-Tile device tx_pll_locked signal fail to assert when OSC_CLK_1 is used as the configuration clock source?

Environment

    Intel® Quartus® Prime Pro Edition
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Description

Due to a problem in the Intel® Quartus® Programmer version 23.3, the Intel Agilex® 7 F-Tile device tx_pll_locked signal fails to assert when the OSC_CLK_1 is used as the configuration clock source.

 

 

Resolution

To work around this problem in the Intel® Quartus® Prime Pro Edition Software version 23.3, install the following patch:

This problem is fixed in the Intel® Quartus® Prime Pro Edition Software version 23.4.

Related Products

This article applies to 1 products

Intel Agilex® 7 FPGAs and SoC FPGAs

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