Article ID: 000097812 Content Type: Troubleshooting Last Reviewed: 06/18/2024

Why does the Siemens* ModelSim* simulation stop unexpectedly when using the SDI II FPGA IP Multi-Rate Parallel loopback without external VCXO design?

Environment

  • Intel® Quartus® Prime Pro Edition
  • SDI II Intel® FPGA IP
    • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    Due to a problem in the Quartus® Prime Pro Edition Software version 23.4, the ModelSim* testbench fails when simulating the SDI II Multi-rate Parallel loopback without external VCXO design. 

    Resolution

    To work around this problem, please update the testbench by connecting the gxb_tx_reconfig_xcvr_clk to the tb_test_control_rx_coreclk.

    This problem is fixed starting with Quartus® Prime Pro Edition Software version 24.1.

    Related Products

    This article applies to 1 products

    Intel Agilex® 7 FPGAs and SoC FPGAs

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