Error: Failure to checkout svverification license feature.

This error will be seen when using Questa*-Intel® FPGA Edition to simulate the Intel Agilex® 7 M-Series FPGA EMIF IP for DDR5 Interfaces design example.

To work around this problem, perform the following steps:

1. Open msim_setup.tcl file under .../sim/ed_sim/mentor folder. 
2. Modify the following command:

            eval vsim -suppress 2732 -suppress 1130 -suppress 7041 -suppress 7033 $elabcommand

            to 

            eval vsim -nocvg -suppress 2732 -suppress 1130 -suppress 7041 -suppress 7033 $elabcommand