Article ID: 000097743 Content Type: Error Messages Last Reviewed: 06/10/2025

Why does Signal Tap show "Program the device to continue" when using the JTAG-Over-Protocol IP to tap logic within a PR (Partial Reconfiguration) partition?

Environment

    Intel® Quartus® Prime Pro Edition
    Signal Tap Logic Analyzer Intel® FPGA IP
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Description

Due to a problem in the Quartus® Prime Pro Edition Software version 23.4 and earlier, the Signal Tap Logic Analyzer IP will show "Program the device to continue" when attempting to tap logic within a PR partition when also using the JTAG-Over-Protocol IP.

Resolution

To work around this problem, disable the Enable use of TCK-ENA option within the JTAG-Over-Protocol IP.

This problem is scheduled to be fixed in a future release of Quartus® Prime Pro Edition Software.

Related Products

This article applies to 1 products

Intel® Stratix® 10 FPGAs and SoC FPGAs

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