Description
Due to a problem in the Intel® Quartus® Prime Prime Pro Edition Software version 23.4 and earlier, the Signal Tap Logic Analyzer Intel® FPGA IP will show "Program the device to continue" when attempting to tap logic within a PR partition when also using the JTAG-Over-Protocol Intel® FPGA IP.
Resolution
To work around this problem, disable the Enable use of TCK-ENA option within the JTAG-Over-Protocol Intel® FPGA IP.
This problem is scheduled to be fixed in a future release of Intel® Quartus® Prime Pro Edition Software.