Article ID: 000097741 Content Type: Troubleshooting Last Reviewed: 12/27/2023

Why does the Debug Toolkit of Intel Agilex® 7 R-Tile Compute Express Link* (CXL*) 1.1/2.0 FPGA IP report transaction timeout in Intel® Quartus® Prime Pro Edition Software Version 23.3?

Environment

  • Intel® Quartus® Prime Pro Edition

    • OS Independent family

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    Description

    Due to a problem in Intel® Quartus® Prime Pro Edition Software version 23.3, you might observe the error message shown below when launching Debug Toolkit of Intel Agilex® 7 R-Tile Compute Express Link* (CXL*) 1.1/2.0 FPGA IP.

    master_read_32: This transaction did not complete in 60 seconds. System Console is giving up.

     

     

    Resolution

    This problem is fixed beginning with the Intel® Quartus® Prime Pro Edition Software version 23.4.

    Related Products

    This article applies to 1 products

    Intel Agilex® 7 FPGAs and SoC FPGAs I-Series

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