Article ID: 000097725 Content Type: Troubleshooting Last Reviewed: 12/28/2023

Why does the tx_pll_locked port fail to assert on the Intel Agilex® 7 F-Tile PMA-based high-speed IP after dynamically reconfiguring the channel to another profile?

Environment

    Intel® Quartus® Prime Pro Edition
    Interfaces
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Description

Due to a problem in the Intel® Quartus® Prime Pro Edition Software version 23.3, the tx_pll_locked port of an Intel Agilex® 7 F-Tile PMA-based high-speed IP may fail to assert after dynamically reconfiguring the channel to another profile.

Resolution

To work around this problem in the Intel® Quartus® Prime Pro Edition Software version 23.3, install the following patch:

This problem has been fixed in release 23.4 of the Intel® Quartus® Prime Pro Edition Software.

Related Products

This article applies to 1 products

Intel Agilex® 7 FPGAs and SoC FPGAs

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