Article ID: 000097694 Content Type: Product Information & Documentation Last Reviewed: 12/19/2023

Why does the configuration time for Intel Agilex® 7 devices increase around 10% when using 4 transceiver tile (F-tile/R-tile) in the design in Intel® Quartus® Prime Pro Edition Software Version 23.4?

Environment

    Intel® Quartus® Prime Pro Edition
    Intel® FPGA Programming Software
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Description

Due to a problem in the Intel® Quartus® Prime Pro Edition Software version 23.4, you may observe that the configuration time for Intel Agilex® 7 devices increases by around 10% compared to previous versions when using 4 transceiver tiles (F-tile/R-tile) in the design.

Resolution

This problem will be fixed in a future release of Intel® Quartus® Prime Pro Edition Software.

Related Products

This article applies to 1 products

Intel Agilex® 7 FPGAs and SoC FPGAs

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