Article ID: 000097682 Content Type: Troubleshooting Last Reviewed: 04/16/2024

Why does the p<n>_ss_app_st_tx_ready signal go to X in simulation of 40GbE and 50GbE Agilex™ 7 F-Tile variants of the Ethernet Subsystem FPGA IP ports when the Enable Preamble Passthrough parameter is selected.

Environment

    Intel® Quartus® Prime Pro Edition
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Description

Due to a problem in the Quartus® Prime Pro Edition Software version 23.4, the p<n>_ss_app_st_tx_ready signal will go to X (undefined) in simulation of 40GbE or 50GbE ports when the Enable Preamble Passthrough parameter is selected on Agilex™ 7 F-Tile variants of the Ethernet Subsystem FPGA IP.

 

Resolution

To workaround this problem in simulation, do not select the Enable Preamble Passthrough parameter for 40GbE or 50GbE ports.

This problem has been fixed in version 24.1 of the Quartus® Prime Pro Edition Software.

Related Products

This article applies to 1 products

Intel Agilex® 7 FPGAs and SoC FPGAs

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