Article ID: 000097681 Content Type: Errata Last Reviewed: 04/15/2024

Why are incorrectly-sized packets transmitted from the Ethernet Subsystem FPGA IP for the Agilex™ 7 F-Tile multi-port variant when the Dynamic Reconfiguration parameter is enabled and the Client Interface parameter is set to MAC Segmented?

Environment

  • Intel® Quartus® Prime Pro Edition
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    Due to a problem in the Quartus® Prime Pro Edition Software version 23.4, incorrectly-sized packets will be transmitted from the multi-port Agilex™ 7 F-Tile variants of the Ethernet Subsystem FPGA IP when both the Dynamic Reconfiguration parameter is enabled and the Client Interface parameter is set to MAC Segmented. This problem will affect all dynamically reconfigurable ports ranging from 50GbE to 400GbE.

     

    Resolution

    There is no workaround for this problem.

    This problem has been fixed starting in version 24.1 of the Quartus® Prime Pro Edition Software.

    Related Products

    This article applies to 1 products

    Intel Agilex® 7 FPGAs and SoC FPGAs