Why does the Ethernet Subsystem FPGA IP Example Design for the Agilex™ 7 F-Tile variant with 40GbE, 50GbE, or 100GbE ports and the Client Interface parameter set to “MAC Avalon ST” fail to function correctly in both simulation and hardware?

Due to a problem in the Quartus® Prime Pro Edition Software version 23.4, the Ethernet Subsystem FPGA IP Example Design for the Agilex™ 7 F-Tile variant with 40GbE, 50GbE or 100GbE ports and the Client Interface parameter set to MAC Avalon ST fails to function correctly in simulation and hardware.

To work around this problem, perform the following steps:

1. Open the file <design example project directory>/hardware_test_design/common_f/hssi_ss_f_packet_client_top.sv
2. Change line 37: 
   • FROM:
     • parameter NUM_SEG = ( CLIENT_IF_TYPE == 1) ? 'd1 : (DATA_WIDTH/64),
   • TO:
     • parameter NUM_SEG = (DATA_WIDTH/64), 
3. Save the file
4. Re-run the Example Design in simulation or hardware

This problem has been fixed starting in version 24.1 of the Quartus® Prime Pro Edition Software.