Why does the External Memory Interfaces Intel® Stratix® 10 FPGA IP not calibrate when it is located in the same column as an IOPLL Intel® FPGA IP and the reference clock of the IOPLL Intel® FPGA IP is not ready?

The IOPLL Intel® FPGA IP will gate the power-up calibration of the External Memory Interfaces Intel® Stratix® 10 FPGA IP if the reference clock of the IOPLL Intel® FPGA IP is not stable.

To work around this problem, follow the steps below:

1. Enable the Connect to an upstream PLL through the Core Clock Network Cascading (create a permit_cal input signal) option in the IOPLL Intel® FPGA IP.
2. Connect the permit_cal input port to 1’b1 in the IOPLL Intel® FPGA IP instance.

The power-up calibration of the External Memory Interfaces Intel® Stratix® 10 FPGA IP will be performed regardless of the status of the IOPLL Intel® FPGA IP reference clock.