Article ID: 000097635 Content Type: Product Information & Documentation Last Reviewed: 12/14/2023

Is en_pfc_port in E-Tile Ethernet IP a read only register?

Environment

BUILT IN - ARTICLE INTRO SECOND COMPONENT
Description

Due to a problem in E-Tile Hard IP User Guide: E-Tile Hard IP for Ethernet and E-Tile CPRI PHY Intel FPGA IPs (UG-20160), en_pfc_port register is wrongly defined as ready only. In fact, it is a read-write register to enable TX PAUSE or TX PFC.

 

Resolution

This problem is currently scheduled to be fixed in a future release of the UG-20160.

Related Products

This article applies to 2 products

Intel Agilex® 7 FPGAs and SoC FPGAs F-Series
Intel® Stratix® 10 TX FPGA

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