What are the special requirements of Intel Agilex® 7 F-Tile devices reference clocks?

The Intel Agilex® 7 F-Tile devices reference clocks have special requirements that users must follow. Otherwise, your design will work abnormally, and transceivers might experience performance degradation.

FHT Reference Clock:

• You must provide a stable and running reference clock to FHT PMA at device configuration. Otherwise, it will cause FHT PMA lane performance degradation.
• Once the FHT reference clock is up, it must be stable and remain active while the device is powered on. Otherwise, it will cause FHT PMA lane performance degradation, and you must reconfigure the device to get the design working normally.
• The FHT reference clock stable definition is specified in Intel Agilex® 7 FPGAs and SoCs Device Data Sheet.

FGT Reference Clock:

• When you check the Refclk #i is available at and after the device configuration parameter in the F-Tile Reference and System PLL Clocks Intel FPGA IP
  • You must provide a stable and running reference clock to FGT at device configuration. Otherwise, it will cause FGT PMA lane performance degradation.
  • Once the FGT reference clock is up, it must be stable and remain active while the device is powered on. Otherwise, it will cause FGT PMA lane performance degradation.
• When you uncheck the Refclk #i is available at and after the device configuration parameter in the F-Tile Reference and System PLL Clocks Intel FPGA IP
  • You can provide a stable and running reference clock to FGT after device configuration. 
  • After the FGT reference clock is up, it can be inactive.
• The FGT reference clock stable definition is specified in Intel Agilex 7 FPGAs and SoCs Device Data Sheet.

System PLL Reference Clock:

• When you check the Refclk #i is available at and after the device configuration parameter in the F-Tile Reference and System PLL Clocks Intel FPGA IP
  • You must provide a stable and running reference clock to the system PLL at device configuration. Otherwise, the system PLL will not lock, and you must reconfigure the device to get the device working normally.
  • Once the system PLL reference clock is up, it must be stable and remain active while the device is powered on. Otherwise, you must reconfigure the device to get the device working normally.
• When you uncheck the Refclk #i is available at and after the device configuration parameter in the F-Tile Reference and System PLL Clocks Intel FPGA IP
  • You can provide a stable and running reference clock to system PLL after device configuration. 
  • Once the system PLL reference clock is up, it must be stable and remain active while the device is powered on. Otherwise, you must reconfigure the device to get the device working normally.
• The System PLL reference clock stable definition
  • Must adhere to the F-Tile FGT Reference Clock Input Specifications specified in Intel Agilex® 7 FPGAs and SoCs Device Data Sheet.
  • Reference clock maximum period jitter must be less than +/-2.5%. 

For more details, please refer to F-Tile Architecture and PMA and FEC Direct PHY IP User Guide.

Users must adhere to the aforementioned requirements without any exceptions.