Starting with version 23.4, the Intel® Quartus® Prime Pro Edition Software will enforce a check for the appropriate.QSF assignment required to constrain the device’s OSC_CLK_1 pin for projects that contain transceivers in the design.
Failure to include this required .qsf constraint will result in an error of the form seen below being created during the fitter stage of the Intel® Quartus® Prime Pro Edition Software compilation.
Error “Intel FPGA IP instantiated in the design require the DEVICE_INITIALIZATION_CLOCK option to be set to either OSC_CLK_1_25MHZ, OSC_CLK_1_100MHZ or OSC_CLK_1_125MHZ. This assignment is missing in the QSF file.”
To avoid this error, you must add an assignment of the following form to your project’s *.qsf file:
set_global_assignment -name DEVICE_INITIALIZATION_CLOCK <OSC_CLK_1_25MHZ, OSC_CLK_1_100MHZ or OSC_CLK_1_125MHZ>
The frequency selected for this assignment must match the frequency you have provided for your device’s OSC_CLK_1 pin.
For example, if you have provided a 125MHz clock on your device’s OSC_CLK_1 pin, the assignment would be as shown below:
set_global_assignment -name DEVICE_INITIALIZATION_CLOCK OSC_CLK_1_125MHZ