Article ID: 000097609 Content Type: Troubleshooting Last Reviewed: 04/16/2024

Why does my Dynamic Reconfiguration project generate a critical warning when the F-Tile Ethernet Multirate FPGA IP has both auto-negotiation and link training enabled?

Environment

  • Intel® Quartus® Prime Pro Edition
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    Description

    Due to a problem in the Quartus®  Prime Pro Edition Software version 23.4, dynamic reconfiguration projects containing the F-Tile Ethernet Multirate FPGA IP with ANLT enabled will generate critical warnings.

    These warnings will be of the form shown below:

    Critical Warning (22976): Dynamic Reconfiguration controller IP specification is missing for IP or IPs {loop_dut[0].u0|eth_f_dr_0|U_base_profile|eth_f_0, loop_dut[0].u0|eth_f_dr_0|U_sec_profile1|sec_profile_1}. Use IP_COLOCATE assignment to specify a Dynamic Reconfiguration controller IP.

     

    Resolution

    To work around this problem, add IP_COLOCATE assignments to your project’s QSF file for the base and each secondary profile of your F-Tile Ethernet Multirate FPGA IP instance. An example of these assignments is shown below:

    set_instance_assignment -name IP_COLOCATE F_TILE -from dr_dut|dr_f_0 -to IP_INST[0].hw_ip_top|dut|eth_f_dr_0|U_base_profile|eth_f_0 -entity eth_f_hw
    set_instance_assignment -name IP_COLOCATE F_TILE -from dr_dut|dr_f_0 -to IP_INST[0].hw_ip_top|dut|eth_f_dr_0|U_sec_profile*|sec_profile_* -entity eth_f_hw

    Where * indicates the number of the secondary profile.

    This problem has been fixed in version 24.1 of the Quartus®  Prime Pro Edition Software.

    Related Products

    This article applies to 1 products

    Intel Agilex® 7 FPGAs and SoC FPGAs