Starting in the Quartus® Prime Pro Edition Software version 23.4, the error below will be seen when using the Agilex™ 7 FPGA F-Tile 200G Hard IP datapath, for example when using the PAM4 8x53Gpbs with QSFPDD Serial loopback design on the Nios® V/m Processor:
Error (24297): Cannot use 200G Hard IP location ehip200g_st_x1_7_rx and FGT channel location fgt_q0_ch0_rx as 200G Hard IP is currently not supported with this OPN. If you need 200G Hard IP, please reach out to Intel Field Representative.
Error: Design cannot be programmed onto available F-Tiles because given location constraints are conflicting, or because the design requires more resources compared to what is available on current device
Starting in the Quartus® Prime Pro Edition Software version 23.4, the F-Tile 200G Hard IP block is de-featured on existing OPNs with no suffix and “B” suffix. For prototyping use only a patch can be provided to enable compilation and SOF file generation.
Please contact your Intel® Field Representative if you require the patch for F-Tile 200G prototype evaluation on OPNs, not including the C suffix.