Article ID: 000097528 Content Type: Troubleshooting Last Reviewed: 12/12/2023

Why does Intel Agilex® 7 R-Tile Compute Express Link* (CXL) 1.1/2.0 FPGA IP not support burst operation on CXL.io Avalon® Memory Mapped Interface?

Environment

  • Intel® Quartus® Prime Pro Edition

    • OS Independent family

    BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    Due to a problem in Intel® Quartus® Prime Pro Edition Software version 23.3 and earlier, the Intel Agilex® 7 R-Tile Compute Express Link* (CXL) 1.1/2.0 FPGA IP doesn't support burst operation on Avalon® Memory Mapped Interface of CXL.io channel.

     

    Resolution

    This problem is scheduled to be fixed in a future release of the Intel® Quartus® Prime Pro Edition Software.

    Related Products

    This article applies to 1 products

    Intel Agilex® 7 FPGAs and SoC FPGAs I-Series

    Need more help?

    Contact support

    Disclaimer

    1

    All postings and use of the content on this site are subject to Intel.com Terms of Use.