Article ID: 000097528 Content Type: Troubleshooting Last Reviewed: 10/06/2025

Why does Agilex™ 7 R-Tile Compute Express Link* (CXL) 1.1/2.0 FPGA IP not support burst operation on CXL.io Avalon® Memory Mapped Interface?

Environment

    Intel® Quartus® Prime Pro Edition

OS Independent family

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Description

Due to a problem in Quartus® Prime Pro Edition Software version 23.3 and earlier, the Agilex™ 7 R-Tile Compute Express Link* (CXL) 1.1/2.0 FPGA IP doesn't support burst operation on the Avalon® Memory Mapped Interface of the CXL.io channel.

 

Resolution

This problem is scheduled to be fixed in a future release of the Quartus® Prime Pro Edition Software.

Related Products

This article applies to 1 products

Intel Agilex® 7 FPGAs and SoC FPGAs I-Series

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