Why does the existing PCI Express* driver fail to access the CSR through the CXL.io path of the Agilex™ 7 R-Tile Compute Express Link* (CXL*) 1.1/2.0 FPGA IP?

Due to a problem in the Quartus® Prime Pro Edition Software version 23.3 and earlier, the default setting of the Device ID(0x0ddb) and Vendor ID(0x8086) in the Agilex™ 7 R-Tile Compute Express Link* (CXL*) 1.1/2.0 FPGA IP does not match the existing PCIe driver (PCIe and CXL.io are the same from the software perspective), which causes the driver loading and CSR access failure.

To work around this problem, change the setting of Device ID(0x0ddb) and Vendor ID(0x8086) in the Agilex™ 7 R-Tile Compute Express Link* (CXL*) 1.1/2.0 FPGA IP beginning with the Quartus® Prime Pro Edition Software version 23.1, or adapt the existing PCI Express* driver to specify the Device ID(0x0ddb) and Vendor ID(0x8086) to match the default setting of the Agilex™ 7 R-Tile Compute Express Link* (CXL*) 1.1/2.0 FPGA IP.