Article ID: 000097417 Content Type: Error Messages Last Reviewed: 06/18/2025

Why does the Quartus® Prime Standard Edition Software version 22.1 downwards show "Error (165012): The DQS pin 'dpclk' has a dual-purpose clock pin delay setting, but it is constrained to a pin at location 'PIN XX' that does not support this setting"?

Environment

    Intel® Quartus® Prime Standard Edition
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Description

Due to a problem in the Quartus® Prime Standard Edition Software version 22.1 downwards, an error is shown when adding the dual-purpose clock input pin delay to the DPCLK pin of the Cyclone® 10 LP FPGA.

 

Resolution

This is scheduled to be fixed in a future release of Quartus® Prime Standard Edition Software.

Related Products

This article applies to 1 products

Intel® Cyclone® 10 LP FPGA

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