Article ID: 000097367 Content Type: Errata Last Reviewed: 06/12/2024

Why did the LPDDR5 Agilex™ 7 FPGA M-Series EMIF IP Design Example fail simulation?

Environment

  • Intel® Quartus® Prime Pro Edition
  • External Memory Interfaces (EMIF) IP
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT

    Critical Issue

    Description

    Due to a problem in Quartus® Prime Pro Edition Software version 23.2,  you may see that the LPDDR5 example design has failed simulation in the Questa* FPGA Edition simulator.

    The same design is passing simulation in the VCS* simulator.

    Resolution

    There is no workaround for this problem. 

    This problem is fixed starting with the Quartus® Prime Pro Edition Software version 23.4