Why does analysis & synthesis fail in the Intel® Quartus® Prime Pro Edition Software when the project contains multiple instances of the E-Tile Hard IP for Ethernet Intel® FPGA IP with Dynamic Reconfiguration(DR) mode?

Due to a problem in the E-Tile Hard IP for Ethernet Intel® FPGA IP. Adding multiple instances of the E-Tile Hard IP for Ethernet Intel® FPGA IP into a project with Dynamic Reconfiguration (DR) mode will cause analysis and synthesis to fail.  Failure is caused by the multiple instances of the IP generating similar file names. Below are examples of the typical error messages that will be observed:

Error(13452): Verilog HDL Module Instantiation error at alt_ehipc3_reset_controller_dr.sv(173): module "alt_ehipc3_reset_controller" has no parameter named "POWER_ON_RESET_EN"

Error(13452): Verilog HDL Module Instantiation error at alt_ehipc3_reset_controller_dr.sv(182): module "alt_ehipc3_reset_controller" has no parameter named "DR_EN"

Error(21358): Verilog HDL error at alt_ehipc3_reset_controller_dr.sv(185): 'clk' is not a port

Error(13305): Verilog HDL error at alt_ehipc3_reset_controller_dr.sv(187): can't find port "i_reserved"

Error(13305): Verilog HDL error at alt_ehipc3_reset_controller_dr.sv(188): can't find port "o_reserved"

Error(13305): Verilog HDL error at alt_ehipc3_reset_controller_dr.sv(189): can't find port "clear_pending_resets"

To workaround this problem in the Intel® Quartus® Prime Pro Edition Software version 22.2 

Download and install patch 0.55 from the following links:

• Intel® Quartus® Prime Pro Edition Software v22.2 Patch 0.55 for Windows (.exe)
• Intel® Quartus® Prime Pro Edition Software v22.2 Patch 0.55 for Linux (.run)
• Readme for Intel® Quartus® Prime Pro Edition Software v22.2 Patch 0.55 (.txt)

This problem has been fixed in version 23.4 of the Intel® Quartus® Prime Pro Edition Software.