Article ID: 000097219 Content Type: Product Information & Documentation Last Reviewed: 11/15/2023

DMA_afu simulation example pCLK is set at 400 MHz instead of 250 MHz

Environment

  • Intel® Acceleration Stack for Intel® FPGA PAC D5005
    • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    The out-of-box simulation runs the pCLK at 400MHz, while in the FPGA Interface Manager Data Sheet, the pCLK is set to 250MHz.

    Resolution

    As ASE is a functional model, changing the pClk frequency won't make performance estimates any more accurate. If the developer still wants to edit the clock’s value, changes need to be made in ASE's rtl/platform.vh in the clock section.

    Related Products

    This article applies to 2 products

    Intel® Programmable Devices
    Intel® FPGA PAC D5005

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