Due to a problem in the Intel® Quartus® Prime Pro Edition Software version 23.3, the PHY Lite for Parallel Interfaces Intel® FPGA IP without dynamic reconfiguration will fail to assert the interface_locked signal in the Intel Agilex® 7 M-Series FPGA.
To work around this problem, turn on dynamic reconfiguration mode in the IP Parameter Editor Pro GUI and instantiate the Intel® FPGA Calibration IP in your RTL design when using the PHY Lite for Parallel Interfaces Intel® FPGA IP in the Intel Agilex® 7 M-Series even if the design does not require dynamic calibration.
Please refer to an example design with dynamic reconfiguration to connect the Intel® FPGA Calibration IP to the PHY Lite for Parallel Interfaces Intel® FPGA IP.
This problem is scheduled to be fixed in a future release of the Intel® Quartus® Prime Pro Edition Software.