Why does the PHY Lite for Parallel Interfaces IP without dynamic reconfiguration in the Agilex™ 7 FPGA M-Series fail to assert interface_locked in the Quartus® Prime Pro Edition Software version 23.3?

Due to a problem in the Quartus® Prime Pro Edition Software version 23.3, the PHY Lite for Parallel Interfaces IP without dynamic reconfiguration will fail to assert the interface_locked signal in the Agilex™ 7 FPGA M-Series.

To work around this problem, turn on dynamic reconfiguration mode in the IP Parameter Editor Pro GUI and instantiate the Calibration IP in your RTL design when using the PHY Lite for Parallel Interfaces IP in the Agilex™ 7 FPGA M-Series, even if the design does not require dynamic calibration.

Please refer to an example design with dynamic reconfiguration to connect the Calibration IP to the PHY Lite for Parallel Interfaces IP.

This problem is scheduled to be fixed in a future release of the Quartus® Prime Pro Edition Software.