Due to a problem in the Intel® Quartus® Prime Pro Edition Software version 23.3, the calibration result will fail when you run the PHY Lite for Parallel Interfaces Intel® FPGA IP with dynamic reconfiguration at 600 MHz interface frequency or lower in the Agilex™ 7 M-Series FPGA.
To work around this problem, for PHY Lite for Parallel Interfaces FPGA IP running at 600 MHz interface frequency or lower in the Agilex™ 7 M-Series FPGA, you need to increase the read_enable_offset parameter by 2 from its default value.
Please refer to the PHY Lite for Parallel Interfaces Agilex™ 7 FPGA IP for M-Series chapter, Section 2.2.1.3 Input Path, Table 10 Allowed values for read_enable_offset based on RcvEn coarse delay.
In the top-level RTL, the read_enable_offset parameter is named GROUP_X_RCVEN_TO_READ_VALID_OFFSET. The IP sets the read_enable_offset parameter to 3 or 4 by default. This value needs to be increased from its default value by 2.