Article ID: 000097176 Content Type: Troubleshooting Last Reviewed: 05/10/2024

Why are AXI Interface Ready-Valid Latency parameters of Content-Addressable Memory FPGA IP within the Memory Subsystem FPGA IP disabled?

Environment

    Intel® Quartus® Prime Pro Edition
BUILT IN - ARTICLE INTRO SECOND COMPONENT
Description

Due to a problem in the Quartus® Prime Pro Edition Software version 23.3, the parameters under the AXI Interface Ready-Valid Latency section are disabled in the Content-Addressable Memory FPGA IP.

Resolution

This problem has been fixed in the Quartus® Prime Pro Edition Software version 23.4.

Related Products

This article applies to 1 products

Intel® Programmable Devices

1

Need more help?

Contact support

Disclaimer

1

All postings and use of the content on this site are subject to Intel.com Terms of Use.