Article ID: 000097173 Content Type: Error Messages Last Reviewed: 10/30/2023

Warning(16735): Verilog HDL warning at ddrx_ropt_ctrl.sv(1821): actual bit length 2 differs from formal bit length 8 for port

Environment

    Intel® Quartus® Prime Pro Edition
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Description

This warning might be seen in the Intel® Quartus® Prime Pro Edition Software version 23.3 when you compile a design containing the Memory Subsystem Intel® FPGA IP that instantiates a Content-Addressable Memory Intel® FPGA IP using the MBL algorithm.

Resolution

It is safe to ignore this warning.
This problem is scheduled to be fixed in a future release of the Intel® Quartus® Prime Pro Edition Software.

Related Products

This article applies to 1 products

Intel® Programmable Devices

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