Incorrect information on the F-Tile SDI II Intel® FPGA IP Design Example User Guide – Subchapter 1.4. Compiling and Testing the Design in Hardware

Due to a mistake in version 2023.4.10 of the F-tile SDI II FPGA IP Design Example User Guide, the information about the position of switches on the development kit is stated under Subchapter 1.4. Compiling and Testing the Design in Hardware at point no. 5 is incorrect.

The correct information about the position of switches on the development kit as below:

Ensure all the switches on the development kit are in their default position. Refer to the Intel Agilex® 7 I-Series Transceiver-SoC Development Kit User Guide for more information.

If you are generating a parallel loopback with an external VCXO design example, toggle DIPSW S10.2 onboard to the OFF position

This updated information will be added in a future release of the F-Tile SDI II Intel® FPGA IP Design Example User Guide.