Why is there a mismatch in the 5G Polar FPGA IP output result between the MATLAB* and RTL simulation model?

Due to a problem with the formatting of input data and parameter data and encoder output data when using the 5G Polar FPGA IP version 2.0.0, you will observe a mismatch in the 5G Polar FPGA IP output result between the MATLAB* and RTL simulation model. 

To work around this problem follow steps detailed below.

1. Start with using the Matlab* example from the user guide polar5g_codec_tb(4,2,4,1) to run Matlab*.
2. Matlab* generates polar5g_enc_in.txt, polar5g_enc_out.txt, and polar5g_codec_param.txt files in the <Design Example Directory>/Matlab/ folder.
3. Modify these 3 files by adding a 0 in the first row of each file as shown below.

For example: 

Below is the generated polar5g_enc_in.txt 

1 1 1 1 0 0 0 0 0 1 1 0 1 0 0 0 1 1 0 0 0 1 1 0 1 1 0 1 1 0 1 0
1 0 0 1 1 1 1 1 1 0 1 0

Modified polar5g_enc_in.txt

0
1 1 1 1 0 0 0 0 0 1 1 0 1 0 0 0 1 1 0 0 0 1 1 0 1 1 0 1 1 0 1 0
1 0 0 1 1 1 1 1 1 0 1 0

4. Copy and paste the modified 3 files into <Design Example Directory>/test_data folder.
5. The default simulation runs 300 frames. So, modify frm_lmt variable in polar5g_enc_tb.sv to 1 frame from the <Design Example Directory>/src folder.
6. Run the RTL simulation.
7. The Matlab* encoder output now matches the RTL output.

#NOTE: The simulation reports failure as the 0 location in the first row of each file is not identical to the location used by MATLAB*. The subsequent 64 bits patterns are the same. This can be manually checked in the polar5g_enc_out.txt file.

This problem is fixed beginning with version 24.1 release of the 5G Polar FPGA IP.