Description
Due to a problem in Quartus® Prime Pro Edition Software version 23.2 and 23.3, you may see timing violations for any of the paths ending as shown below when migrating F-Tile Avalon® Streaming FPGA IP for PCI Express* from Quartus® Prime Pro Edition Software version 23.1 to 23.2 or 23.3 in Agilex™ 7 devices.
- *|hdpldadapt_tx_chnl_*~pld_tx_clk1_dcm.reg
- *|cur_state*|din_s1
- *|pcie_src_inst|p*_hot_rst_cur_state[*]
- *|pcie_src_inst|in_warm_rst_inst|*
Resolution
To workaround this problem, add the following set_false_path to the top SDC file, which will fix the timing violations:
- set_false_path -from [get_keepers ${ip_inst_name}|pcie_sip_top_inst|pcie_src_inst|pld_adapter_tx_pld_rst_n_r_ch*[*]] -to [get_keepers *auto_tiles|z1577*|hdpldadapt_tx_chnl_*~pld_tx_clk1_dcm.reg]
- set_false_path -from [get_keepers ${ip_inst_name}|pcie_sip_top_inst|pcie_src_inst|pld_adapter_rx_pld_rst_n_r_ch*[*]] -to [get_keepers *auto_tiles|z1577*|hdpldadapt_rx_chnl_*~pld_rx_clk1_dcm.reg]
- set_false_path -from [get_keepers ${ip_inst_name}|pcie_sip_top_inst|pcie_src_inst|pld_adapter_rx_pld_rst_n_r_ch*[*]] -to [get_keepers *auto_tiles|z1577*|hdpldadapt_tx_chnl_*~pld_tx_clk1_dcm.reg]
- set_false_path -from [get_keepers ${ip_inst_name}|pcie_sip_top_inst|pcie_src_inst|cur_state*] -to [get_keepers ${ip_inst_name}|pcie_sip_top_inst|pcie_src_inst|cur_state*|din_s1]
- set_false_path -from [get_keepers ${ip_inst_name}|pcie_sip_top_inst|pcie_src_inst|cur_state*] -to [get_keepers ${ip_inst_name}|pcie_sip_top_inst|pcie_src_inst|p*_hot_rst_cur_state[*]]
- set_false_path -from [get_keepers ${ip_inst_name}|pcie_sip_top_inst|pcie_src_inst|in_warm_rst*] -to [get_keepers ${ip_inst_name}|pcie_sip_top_inst|pcie_src_inst|in_warm_rst_inst|*]
This problem is fixed beginning with the Quartus® Prime Pro Edition Software version 23.4.