Due to a problem in the Clock Controller GUI of the Agilex™ 7 FPGA I-Series Transceiver-SoC Development Kit, the F-tile Serial Lite IV IP Design Example fails when you need to configure the OUT1 clock frequency of the chip Si5332. This is because there is a problem with this Si5332 GUI; the OUT1 frequency can not be accurately configured.
Similar failures might be seen for all Agilex™ 7 F-tile IP designs if you use the Agilex™ 7 FPGA I-Series Transceiver-SoC Development Kit, your design utilizes the Si5332 OUT1 clock, and the default frequency, 166.66 MHz, needs to be changed.
To work around this problem, you should avoid setting the Si5332 OUT1 frequency directly using the "set" button. You need to use the "import" button to accurately set the Si5332 OUT1 clock frequency.
ClockBuilder Pro software can export the import function of a TXT file. A sample si5332 project and a si5332-project.txt file are attached for reference.
This problem will be fixed in a future release of the Quartus® Prime Pro Edition Software.