Article ID: 000096871 Content Type: Errata Last Reviewed: 04/16/2024

Why does the Quartus® Prime Pro, Support Logic Generation stage fail in a design with multiple instances of the F-Tile Ethernet Multirate FPGA IP when the option Enable dedicated CDR clock output has been selected?

Environment

  • Intel® Quartus® Prime Pro Edition
    • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    Due to a problem in the Quartus® Prime Pro Edition Software version 23.3, the Support Logic Generation stage of compilation will fail in a design with multiple instances of the F-Tile Ethernet Multirate FPGA IP if the variants have enabled the Enable dedicated CDR clock output option.

     

    Resolution

    There is no workaround for this problem.

    This problem has been fixed in version 23.4 of the Quartus® Prime Pro Edition Software.

    Related Products

    This article applies to 1 products

    Intel Agilex® 7 FPGAs and SoC FPGAs

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