When using the F-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* Design Example, the following following restrictions apply:
PIO Design Example:
For this PIO design example, there is no support for the back-to-back TLP packets from the host processor.
The design example is intended to handle simple read-write instructions based on the TLP command. TLP transaction of memory write request (MWr) and write the data to the MEM device. As for the TLP transaction of memory read request (MRd), the design will read the data from the MEM device and return completion with data (CplD).
Note: This design example does not include the full feature of the F-Tile Avalon® Streaming Intel® FPGA IP for PCI Express*. Hence, it is not suitable for customer design reference.
SR-IOV Design Example:
For the SR-IOV design example, there is no support for the back-to-back TLP packets from the host processor.
The design is intended to handle simple read-write instructions based on the TLP command. TLP transaction of memory write request (MWr) and write the data to the designated RAM memory space. As for the TLP transaction of memory read request (MRd), the design will read the data from RAM memory space and return completion with data (CplD).
No upstream request from the SR-IOV APPS. The data and address requested to access the SR-IOV APPS must be DW-aligned. The maximum data transfer is 128bit.
The F-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* Design Example capabilities are not scheduled to be improved.