Article ID: 000096580 Content Type: Troubleshooting Last Reviewed: 11/23/2024

Why does the O-RAN FPGA IP have a missing IQ sample and asserted error register after processing a valid U-Plane data packet through the receiver transport interface?

Environment

  • Intel® Quartus® Prime Pro Edition
  • Interfaces
    • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    Due to a problem in the O-RAN FPGA IP version 1.9.1 and earlier, you may see the O-RAN FPGA IP had a missing IQ sample and asserted error register after processing valid U-Plane data packet through the receiver transport interface.

    Resolution

    This problem is fixed in the 2.0.0 version of the O-RAN FPGA IP Webcore.

    Related Products

    This article applies to 8 products

    Intel Agilex® 7 FPGAs and SoC FPGAs
    Intel® Arria® 10 FPGAs and SoC FPGAs
    Intel® Stratix® 10 DX FPGA
    Intel® Stratix® 10 GX FPGA
    Intel® Stratix® 10 MX FPGA
    Intel® Stratix® 10 NX FPGA
    Intel® Stratix® 10 SX SoC FPGA
    Intel® Stratix® 10 TX FPGA

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