Article ID: 000096578 Content Type: Troubleshooting Last Reviewed: 04/17/2024

Why is the O-RAN FPGA IP reset polarity is inverted in platform designer?

Environment

  • Intel® Quartus® Prime Pro Edition
  • Interfaces
    • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    Due to a problem in the O-RAN FPGA IP version 1.9.1 and earlier, the input reset signal maps to incorrect polarity when instantiated in Platform Designer. As the input reset to the O-RAN FPGA IP is active low, Platform Designer should automatically map the signal type to reset_n instead of type reset.

    Resolution

    To work around  this problem, perform the following steps:

    1). Open the oran_hw.tcl file available at <quartus_instalation_dir>/ip/altera_cloud/oran/src/.

    2). Find and replace the following lines of code: 

    a). From add_interface_port rst_tx_n rst_tx_n reset INPUT 1
         To add_interface_port rst_tx_n rst_tx_n reset_n INPUT 1.

    b). From add_interface_port rst_rx_n rst_rx_n reset INPUT 1
         To add_interface_port rst_rx_n rst_rx_n reset_n INPUT 1

    c). From add_interface_port rst_csr_n rst_csr_n reset INPUT 1
         To add_interface_port rst_csr_n rst_csr_n reset_n INPUT 1

     

    Related Products

    This article applies to 9 products

    Intel Agilex® 7 FPGAs and SoC FPGAs F-Series
    Intel Agilex® 7 FPGAs and SoC FPGAs I-Series
    Intel® Arria® 10 FPGAs and SoC FPGAs
    Intel® Stratix® 10 DX FPGA
    Intel® Stratix® 10 GX FPGA
    Intel® Stratix® 10 MX FPGA
    Intel® Stratix® 10 NX FPGA
    Intel® Stratix® 10 SX SoC FPGA
    Intel® Stratix® 10 TX FPGA

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