Article ID: 000096577 Content Type: Troubleshooting Last Reviewed: 11/29/2023

Why is the eCPRI Intel® FPGA IP reset polarity inverted in platform designer?

Environment

  • Intel® Quartus® Prime Pro Edition
  • Intel® CPRI
    • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    Due to a problem in the eCPRI Intel® FPGA IP version 2.0.4 and earlier, the input reset signal maps to incorrect polarity when instantiated in Platform Designer. The input reset to the eCPRI Intel® FPGA IP is active low, Platform Designer should automatically map the signal type to "reset_n" instead of reset.

     

     

    Resolution

    To work around  this problem,  perform the following steps:

    1). Open the ecpri_interface.tcl file available at <quartus_instalation_dir>/ip/altera_cloud/ecpri/ecpri_hw_tcl/.

    2). Find and replace the following line: 

         From add_interface_port $port_name $port_name reset input 1
         To add_interface_port $port_name $port_name reset_n input 1

    This problem has been fixed starting in version 23.3 of the eCPRI Intel® FPGA IP webcore.

    Related Products

    This article applies to 9 products

    Intel® Stratix® 10 DX FPGA
    Intel® Stratix® 10 GX FPGA
    Intel® Stratix® 10 MX FPGA
    Intel® Stratix® 10 NX FPGA
    Intel® Stratix® 10 SX SoC FPGA
    Intel® Stratix® 10 TX FPGA
    Intel Agilex® 7 FPGAs and SoC FPGAs F-Series
    Intel Agilex® 7 FPGAs and SoC FPGAs I-Series
    Intel® Arria® 10 FPGAs and SoC FPGAs

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