Why does Intel Agilex® 7 FPGA LPDDR5 error out in Intel® Quartus® Prime Pro Edition Software version 23.2 with calibration failures?

To work around this problem, ignore the error in Intel Agilex® 7 LPDDR5 Mem Device IP when changing the read latency from the auto-computed value from 9 cycles to 10 cycles because you can actually select "Save Configuration" even with errors outstanding Or Increment the Write Latency from 8 to 9.

This issue is fixed beginning with Intel® Quartus® Prime Pro Edition Software version 23.3. Users are able to generate designs with WDBI correctly enabled using default read/write latencies.
However, users cannot use custom read/write latencies beyond what is in the JEDEC tables.