Why does the R-Tile Intel® FPGA IP for Compute Express Link* (CXL*) Type3 Design Example report UVM_FATAL message when running simulation?

Due to a problem in the Intel® Quartus® Prime Pro Edition Software version 23.1, you might observe the following error message when running the simulation of the R-Tile Intel® FPGA IP for Compute Express Link* (CXL*) Type3 Design Example:

UVM_FATAL /cxltyp3ddr_tb_23p1_acs/tb/verif/tb_top/cxl_tb_top.sv(255)  @ 1000000.000ns: reporter [cxl_tb_top_initialize] Gen5 linkup failed.  Timeout!!!!

To work around this problem, update a newer version of Avery BFM and install a patch for the Intel® Quartus® Prime Pro Edition Software version 23.1. 

1. Update Avery BFM version to apciexactor-2.5b.cxl;
2. Download and install patch 0.08 from the following links:

• Intel® Quartus® Prime Pro Edition Software v23.1 Patch 0.08 for Windows (.exe)
• Intel® Quartus® Prime Pro Edition Software v23.1 Patch 0.08 for Linux (.run)
• Readme for Intel® Quartus® Prime Pro Edition Software v23.1 Patch 0.08 (.txt)

  This problem is fixed beginning with the Intel® Quartus® Prime Pro Edition software version 23.2.