How can the figures of "Table 89. IOE Programmable Delay for the Arria® 10 FPGA Devices" be understood in the Arria® 10 FPGA Device Datasheet?

1. In versions before 2024.07.08 of Arria® 10 FPGAs Core Fabric and General Purpose I/Os Handbook, Chapter 5.5.3.3. Programmable IOE Delay, the sentence in the Arria®10 FPGAs GPIO handbook mentioning “50 ps incremental delays” is not an exact value. It is only an example explaining the relationship between "Offset" values and "Maximum Delay." Users should refer to the Datasheet for exact IOE delay values.
2. In the Arria® 10 Device Datasheet, Table 89 shows the Maximum Delay value of different Speed Grades and the Offset value range for input and output pins. But the table does not exactly explain their relationships. 

In versions before 2024.07.08 of Arria® 10 FPGAs Core Fabric and General Purpose I/Os Handbook, 5.5.3.3. The Programmable IOE Delay chapter contains a sentence mentioning “50 ps incremental delays”. It is not an exact value, but only an example explaining the relationship between "Offset" values and "Maximum Delay". Users should refer to the Datasheet for exact IOE delay values.

From the Arria® 10 FPGA Device Datasheet Table 89. IOE Programmable Delay for the Arria® 10 FPGA Devices, we can see different maximum IOE delays for devices with different speed grades. We can adjust the Output Delay Chain Setting (IO_IN_DLY_CHN) for the output path from 0~15, which means a 15-divided resolution. For the Input path, the Input Delay Chain Setting (IO_OUT_DLY_CHN) parameter range is 0~63, 63-divided resolution.

Simplified the sentence to formulas as below:

For the output pin, if we set the IO_OUT_DLY_CHN as N,

Output path incremental delay = Maximum output delay / 15

Output delay value = Output path incremental delay × N 

For the input pin, if we set the IO_IN_DLY_CHN as N,

Input Path incremental delay =  Maximum output delay / 63

Input delay value = Input path incremental delay × N

For example, the slow model -E3S input delay can be set between 0 and 6.035 ns, with a step size of 6.035 ns/63=0.0958 ns.

However, we must know that PVT does not compensate for IO delay chains. The value changes with Process, Voltage, and Temperature.

In the revision 2024.07.08 of the Arria® 10 FPGAs Core Fabric and General Purpose I/Os Handbook, the description of the IOE delay in chapter 5.5.3.3. Programmable IOE Delay has been updated.