- The sentence in the Intel® Arria®10 GPIO handbook mentioning “50 ps incremental delays” is not an exact value. It is only an example explaining the relationship between "Offset" values and "Maximum Delay." Users should refer to Datasheet for exact IOE delay values.
- In Intel® Arria® 10 Device Datasheet, Table 89 shows the Maximum Delay value of different Speed Grades and the Offset value range for input and output pins. But the table does not exactly explain their relationships.
In Intel® Arria® 10 Core Fabric and General Purpose I/Os Handbook Chapter 5.5.3.3. Programmable IOE Delay, there's a sentence mentioning “50 ps incremental delays”. It is not an exact value, but only an example explaining the relationship between "Offset" values and "Maximum Delay". Users should refer to Datasheet for exact IOE delay values.
From Intel® Arria® 10 Device Datasheet Table 89. IOE Programmable Delay for Intel® Arria® 10 Devices, we can see that there are different maximum IOE delays to devices with different speed grades. We can adjust the Output Delay Chain Setting (IO_IN_DLY_CHN) for the output path from 0~15, which means a 16-divided resolution. For the Input path, the Input Delay Chain Setting (IO_OUT_DLY_CHN) parameter range is 0~63, 64-divided resolution.
Simplified the sentence to formulas as below:
For the output pin, if we set the IO_OUT_DLY_CHN as N,
Output path incremental delay = Maximum output delay / 16
Output delay value = Maximum output delay / 16 × (N + 1)
For the input pin, if we set the IO_IN_DLY_CHN as N,
Input Path incremental delay = Maximum output delay / 64
Output delay value = Maximum output delay / 64 × (N + 1)
For example, the slow model -E3S input delay can be set within a range of 0-6.035 ns, with a step size of 6.035 ns/64=0.0943 ns.
However, we must be aware that IO delay chains are not PVT compensated. The value changes with Process, Voltage, and Temperature.