Description
Due to a problem in the Quartus® Prime Pro Edition Software version 23.2 and earlier, you might see this error during the fitter place stage when targetting Agilex™ 7 I-Series and M-Series FPGAs using the R-Tile FPGA IP for Compute Express Link* (CXL*). This error occurs when the nPERST signal is connected to the FPGA soft logic fabric. The logic in the core must be driven by another signal.
Resolution
To work around this problem, modify the design to make the nPERST pin only drive to the R-Tile PCIe* IP
This problem is fixed beginning with the Quartus® Prime Pro Edition Software version 23.3