Why do I see timing violations in the F-Tile Reference and System PLL Clocks Intel FPGA IP when using Intel® Quartus® Prime Pro Edition Software version 23.2 in Intel Agilex® 7 devices?

Due to a problem in the Intel® Quartus® Prime Pro Edition Software version 23.2 of the F-Tile Reference and System PLL Clocks Intel® FPGA IP for Intel Agilex® 7 devices, you may see timing violations similar to the following.

Slack                      -2.925

From Node          pll|systemclk_f_0|x_sip|d_cnoc_0_count[5]

To Node               pll|systemclk_f_0|x_sip|d_refclk_0_count[2]

Launch Clock      altera_int_osc_clk

Latch                     Clock top_auto_tiles|z1577b_x5_y0_n0|hdpldadapt_rx_chnl_21~maib_ss_lib/s0_170_1__core_periphery__data_to_core[63]

Relationship       0.800

Clock Skew          -2.673

Data Delay           1.027

The timing violation may be seen when unticking the “Refclk #i is active at and after device configuration” options on the F-Tile Reference and System PLL Clocks Intel® FPGA IP.

A patch is available to fix this problem for the Intel® Quartus® Prime Pro Edition Software version 23.2. Download and install patch 0.17 from the following links:

• Intel® Quartus® Prime Pro Edition Software v23.2 Patch 0.17 for Windows (.exe) 
• Intel® Quartus® Prime Pro Edition Software v23.2 Patch 0.17 for Linux (.run) 
• Readme for Intel® Quartus® Prime Pro Edition Software v23.2 Patch 0.17 (.txt) 

This problem is scheduled to be fixed in a future version of the Intel® Quartus Prime Pro Edition Software.