"Error (10228): Verilog HDL error at altpcie_a10_hip_pipen1b_<ip_module_name>.v(4823): module "ip_module_name" cannot be declared more than once, occurs when PCIe hard IP assigns more than 1."

Due to a problem in the Quartus® Prime Standard Edition Software version 21.1 onwards. the following error will occur during Analysis & Synthesis when Arria® 10 Avalon® Streaming Interface for PCI Express* IP or Arria® 10 Avalon® Memory Mapped Interface for PCI Express* IP are implemented more than 1. 

• Error (10228): Verilog HDL error at altpcie_a10_hip_pipen1b_<ip_module_name>.v(4823): module "ip_module_name" cannot be declared more than once occur when PCIe hard IP assign more than 1.

This error is caused by the input pin:perst are connected to both PCIe instances that lead into the instances. To avoid this error, the input pin: perst should be connected to only one PCIe instance. Modify the testing_top.v by adding a new input pin:perst1, and connecting to another PCIe instance.

This problem is fixed beginning with version 23.1 of the Quartus® Prime Standard Edition Software.