Article ID: 000095615 Content Type: Error Messages Last Reviewed: 05/20/2024

Internal Error: Sub-system: TILEIP, File: /quartus/db/tileip/tileip_writer.cpp, Line:3784

Environment

    Intel® Quartus® Prime Pro Edition

Windows 11, 64-bit*

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Description

The F-Tile Low Latency 50G Ethernet FPGA Soft-IP will fail to compile due to the use of a "vsr-mode=VSR_MODE_LOW_LOSS" constraint, causing a compilation error in the Quartus® Prime Pro Edition Software version 23.2.

Below are the error snapshots.

Resolution

To workaround this problem, change the alt_e50_f_hw.qsf  setting as vsr_mode=VSR_MODE_LOW_LOSS in the Quartus® Prime Pro Edition Software version 23.2.

Related Products

This article applies to 2 products

Intel Agilex® 7 FPGA I-Series Development Kits
Intel Agilex® 7 FPGAs and SoC FPGAs

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