Why does the design example for an F-Tile variant with FHT ports enabled within the Ethernet Subsystem Intel® FPGA IP fail to function properly when targeted to the Intel Agilex® 7FPGA I-Series Transceiver-SoC Development Kit (4x F-Tile)?

Due to a problem in the Intel® Quartus® Prime Pro Edition Software version 23.2,  the design example for an F-Tile variant with FHT ports enabled within the Ethernet Subsystem Intel® FPGA IP will fail to function correctly when targeted to an Intel Agilex® 7 FPGA I-Series Transceiver-SoC Development Kit (4x F-Tile).

To workaround this problem, perform the steps shown below:
1.)    Open the hw_hssi_ss_f_top.qsf file found in the <example design project name>/hardware_test_design directory
2.)    Change the pin assignment for i_clk_ref[0] as follows:

FROM: set_location_assignment PIN_R14 -to i_clk_ref[0]

TO:  set_location_assignment PIN_P13 -to i_clk_ref[0]

3.)    Re-compile your project in the Intel® Quartus® Prime Pro Edition software
4.)    Use the development kit’s Clock Controller GUI to set the value of Si5394 (U118), OUT3 to 156.25MHz
5.)    Program your project onto the development kit

This problem was fixed in version 23.3 of the Intel® Quartus® Prime Pro Edition Software.