Why does my E-Tile variant with Dynamic Reconfiguration enabled within the Ethernet Subsystem FPGA IP fail to simulate correctly with the Synopsys* VCS simulator?

Due to a problem in the Quartus® Prime Pro Edition Software version 23.2, E-tile variants with Dynamic Reconfiguration enabled within the Ethernet Subsystem FPGA IP will fail to simulate correctly when using the Synopsys* VCS simulator. The simulation will fail to complete.

This problem does not affect other supported simulation tools.

To workaround this problem, add the “-debug_access+all” switch to the USER_DEFINED_ELAB_OPTIONS section of the “run_vcs.sh” file contained in the <example design project name>/example_testbench directory.

This problem has been fixed in version 24.2 of the Quartus® Prime Pro Edition software.