Article ID: 000095508 Content Type: Error Messages Last Reviewed: 06/28/2023

Why does the L-Tile/H-Tile Transceiver Native PHY Intel® Stratix® 10 FPGA IP Design Example generation fail?

Environment

    Intel® Quartus® Prime Pro Edition
    L-Tile H-Tile Transceiver Native PHY Intel® Stratix® 10 FPGA IP
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Description

Due to a problem in the Intel® Quartus® Prime Pro Edition Software version 23.1 and earlier, generation of the L-Tile/H-Tile Transceiver Native PHY Intel® Stratix® 10 FPGA IP design example can fail even when using the default configuration.

 

 

Resolution

This problem is fixed in the Intel® Quartus® Prime Pro Edition Software version 23.2.

Related Products

This article applies to 1 products

Intel® Stratix® 10 FPGAs and SoC FPGAs

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