Article ID: 000095357 Content Type: Troubleshooting Last Reviewed: 08/02/2023

Why is the interrupt signal on 16550 Compatible UART Intel® FPGA IP asserted right after reset releases?

Environment

  • Intel® Quartus® Prime Standard Edition
  • 16550 Compatible UART Intel® FPGA IP
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    Description

    Due to a problem with Intel® Quartus® Prime Standard Edition Software version 21.1 and 21.1.1,  ier_dlh Interrupt signals on 16550 Compatible UART Intel® FPGA IP are asserted right after reset releases.

     

     

    Resolution

    To work around this problem, there are two options:

    1. Use Intel® Quartus® Prime Standard Edition Software version 22.1 or later versions because the problem has been fixed in Intel® Quartus® Prime Standard Edition Software version 22.1.

    2. Read rbr_thr_dll register, then the interrupt signal will be cleared.

    Related Products

    This article applies to 13 products

    Intel® Cyclone® 10 LP FPGA
    Intel® MAX® CPLDs and FPGAs
    Stratix® FPGAs
    Stratix® II FPGAs
    Stratix® III FPGAs
    Stratix® IV FPGAs
    Stratix® V FPGAs
    Intel® Arria®
    Cyclone® FPGAs
    Cyclone® II FPGAs
    Cyclone® III FPGAs
    Cyclone® IV FPGAs
    Cyclone® V FPGAs and SoC FPGAs

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