Regarding the device configuration with a compressed bitstream, refer to Table 57 in the Cyclone® V FPGA Device Datasheet, which states the clock frequency reductions that are required.
The FPP configuration time is dependant on the DCLK to DATA ratio and the compression percentage.
The following example shows an easy way to calculate the configuration time for compression and uncompressed file:
Let’s say for no compression file 100%, ratio = 1, configuration time = 100*1 = 100 clock
For 50% compression file, ratio = 4, the configuration time = 50*4 = 200 clock (50% compression take double of config time than no compression)
For 25% compression file, ratio = 4, the configuration time = 25*4 = 100 clock (same config time with no compression)
In summary, you will need to compress <25% to achieve less configuration time than without compression file for FPP 16 bit wide.
For AS mode, Cyclone® V FPGAs do not have DCLK to DATA ratio, you can calculate based on the file size by monitoring the nSTATUS high to CONF_DONE to compare between compressed and uncompressed bitstream.