Article ID: 000095018 Content Type: Error Messages Last Reviewed: 05/10/2024

Error(22728): Synthesis is run on design with Tile IP for instance <...> but the support logic has not been generated.

Environment

  • Intel® Quartus® Prime Pro Edition
    • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    You might see this error message at the Synthesis stage when the design uses the .bdf file to instantiate the Tile IP.

    Resolution

    To avoid this error, use a Verilog or VHDL file to instantiate the TIle IP.

    The .bdf file is not supported to instantiate the Tile IP. 

     

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