Why do the Intel Agilex® 7 DDR4 IP EMIF Traffic Generator 2 idle cycle count and loop idle counter have a mismatch ?

Due to a problem in the Intel® Quartus® Prime Pro Edition Software version 20.4 and earlier, the number of idle cycles between successive loops in the EMIF Traffic Generator 2.0 (TG2) does not equal the loop idle counter when the number of reads or writes is 1. This problem only occurs when the number of loops is greater than 2 as reloading the loop idle counter is done incorrectly. The number of idle cycles between loops is one less than the loop idle counter.

This problem is fixed in the Intel® Quartus® Prime Pro Edition Software version 21.1 onwards.