Error (14394):  Verilog HDL error at <project_name>_auto_tiles.sv(<line number>) : <ip instance_name> is not declared under the prefix "<top_level_wrapper_name>"

Due to a problem in the Quartus® Prime Pro Edition Software version 23.2 and earlier, you might see this error when your HDL code has a generated block to choose between the instantiation of a design targeted to Agilex™ 7 F-Tile device and other supported device.

If the 'generate if' blocks are not labeled, the cross-module references into unlabelled generate blocks throw an error.

For example

generate 
  if(Agilex == 0)
  begin
  ...
  end
else 
  begin
  ...
end
endgenerate

This error occurs at the Analysis and Synthesis stage.

To work around this problem, define a label for each 'if and else' statement in Verilog HDL and a 'generate' statement in VHDL. For example, if a design is targeted to choose between the Agilex™ F-Tile device and Arria® 10 device, then the instantiation can be chosen using generate statement in Verilog HDL and VHDL as follows.

Verilog HDL
  generate 
    if(Agilex == 0)
    begin : label1_notfor_AG
    ...
    end
  else 
    begin : label2_for_AG
    ...
  end
  endgenerate
  
VHDL
  label: 
  if cond1 generate
    ...  
  elsif cond2 generate  
    ...  
  else generate
    ...  
  end generate label;